電源電壓抑制比

${\displaystyle \mathrm {PSRR} [\mathrm {dB} ]=20\log _{10}\left({\Delta V_{\mathrm {supply} } \over {\Delta V_{\mathrm {out} }}}\right){\mbox{dB}}}$

${\displaystyle \mathrm {PSRR} [\mathrm {dB} ]=20\log _{10}\left({\Delta V_{\mathrm {supply} } \over {\Delta V_{\mathrm {out} }}}\cdot A_{v}\right){\mbox{dB}}}$

${\displaystyle 100\ \mathrm {dB} -40\ \mathrm {dB} =60\ \mathrm {dB} }$.

${\displaystyle 1\ \mathrm {V} \cdot 10^{\frac {-60}{20}}=.001\ \mathrm {V} =1\ \mathrm {mV} }$

參考

1. ^ Allen, Phillip; Hpolberg, Douglas, CMOS Analog Circuit Design, Oxford University Press, Inc, cc 1987.
2. ^ Franco, Design With Operational Amplifiers and Analog Integrated Circuits, McGraw-Hill, Inc, cc 1988.

外部連結

1.Operational Amplifier Power Supply Rejection Ratio (PSRR) and Supply Voltages by Analog Devices, Inc. Definition and measurement of PSRR. http://www.analog.com/static/imported-files/tutorials/MT-043.pdf

2.Testing an A/D's power supply rejection ratio by Rob Reeder, Senior design engineer, Analog Devices Inc., Multi-Chip Products Group, Greensboro, N.C. http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=12804251[永久失效連結]